Semiconductor devices adapted to detect a physical quantity distribution and which include a plurality of unit components (e.g., pixels) arranged in lines or in a matrix are used in a variety of fields. These unit components are responsive to externally supplied electromagnetic wave such as light or radiation.
In the field of video equipment, for example, CCD (Charge Coupled Device), MOS (Metal Oxide Semiconductor) and CMOS (Complementary Metal-oxide Semiconductor) solid-state imaging devices are used to detect light of all physical quantities (example of electromagnetic waves). In these solid-state imaging devices, a physical quantity distribution, converted into an electric signal by the unit components (pixels, in the case of solid-state imaging device), is read out as an electric signal.
On the other hand, some solid-state imaging devices are amplifying solid-state imaging devices. Such solid-state imaging devices have pixels each of which includes an amplifying solid-state imaging element (also referred to as Active Pixel Sensor or APS). An APS has an amplifying drive transistor in a pixel signal generation section adapted to generate a pixel signal commensurate with the signal charge generated by a charge generation section. For example, many CMOS solid-state imaging devices are configured in this manner.
In order to read out a pixel signal from an amplifying solid-state imaging device configured as described above, a pixel section having a plurality of unit pixels arranged therein is address-controlled so that a signal from a given unit pixel can be arbitrarily selected and read out. That is, an amplifying solid-state imaging device is an example of an address-controlled solid-state imaging device.
In an amplifying solid-state imaging element which is an example of an X-Y address solid-state imaging element in which unit pixels are arranged in matrix, for example, a pixel includes MOS-structured or other active elements (MOS transistors) to provide the pixel itself with amplifying capability. That is, a signal charge (photoelectrons) accumulated in a photodiode, i.e., a photoelectric conversion element, is amplified by the active element and read out as image information.
In this type of X-Y address solid-state imaging element, for example, many pixel transistors are arranged in a two-dimensional matrix form to make up a pixel section. The accumulation of a signal charge commensurate with the incident light begins on a line-by-line or pixel-by-pixel basis. The current or voltage signal based on the accumulated signal charge is read out from each pixel through address specification. Here, in MOS (including CMOS) type, column readout scheme (column parallel output scheme) is often used as an example of address control. The column readout scheme is designed to access a row of pixels at the same time, thus reading out a pixel signal from the pixel section on a row-by-row basis. The analog pixel signal read out from the pixel section is converted as necessary into digital data by an analog-to-digital converter (ADC). Therefore, a variety of arrangements for AD conversion have been proposed.
Various schemes have been devised as an AD conversion scheme from the viewpoint of circuit scale, processing speed (speedup), resolution and other factors. The reference signal comparison AD conversion scheme (refer to Patent Document 1) is an example of such various schemes. It should be noted that the reference signal comparison scheme is also referred to as the slope integration or ramp signal comparison scheme. The reference signal comparison AD conversion scheme uses a so-called ramped reference signal (ramp wave) for comparison with the voltage to be converted into digital data. The value of the ramped reference signal changes gradually. The analog unit signal and reference signals are compared. At the same time, the counting is performed during a counting enabled period based on the comparison result, thus acquiring digital data of the unit signal based on the count value. By using a scheme combining the reference signal comparison AD conversion scheme and the column readout scheme (referred to as the column AD scheme) described earlier, it is possible to achieve AD conversion of the analog outputs from the pixels in a column parallel manner at a low frequency band. Therefore, it can be said that this scheme is appropriate for image sensors which combine high image quality and high speed.
For example, recent years have witnessed widespread use of CMOS sensors in mobile phones, digital cameras (compact types and upscale single lens reflex types), camcorders, monitoring cameras, guiding devices and others for their superiority in terms of low power consumption and high speed. Further, CMOS sensors offering high performance and high image quality have come along lately. These CMOS sensors are integrated into a single chip with functional circuit blocks for image processing and other purposes. The reference signal comparison AD conversion scheme is probably applicable to such CMOS sensors.
FIG. 18 is a diagram illustrating a configuration example of a conventional solid-state imaging device 1Z using the reference signal comparison AD conversion scheme. The solid-state imaging device 1Z includes a pixel array section 10, horizontal scan section 12, vertical scan section 14, PLL circuit 20x, system control unit 20y adapted to control the solid-state imaging device 1Z as a whole, column AD conversion section 26, reference signal generation section 27 adapted to generate a reference signal SLP_ADC, sense amplifier 28a, signal processing/interface section 28z and other components. The pixel array section 10 includes unit pixels 3 arranged in a two-dimensional matrix form. The PLL circuit 20x generates an internal clock CKX based on an externally supplied basic clock CK, supplying the internal clock CKX to the reference signal generation section 27 and a counter section 254.
The column AD conversion section 26 includes a comparison section 252 and the counter section 254 for each column. As an example, the counter section 254 is a ripple counter with 13 stages of latches LT_00 to LT_12 connected in series. Further, the counter section 254 is a 13-bit counter that can be switched between up-counting and down-counting modes.
Data D0 to D12 output from the counter section 254 is transmitted to the sense amplifier 28a via horizontal signal lines 18 at a small amplitude level (e.g., several 100 mVp-p). The sense amplifier 28a amplifies the data D0 to D12 having a small amplitude level to a logic level (e.g., 2 to 3 Vp-p), delivering the data to the signal processing/interface section 28z. The signal processing/interface section 28z performs predetermined digital signal processing on the 13-bit data D0 to D12, changing this data into 12-bit output data Dout (D0 to D11) and delivering the data to the unshown circuit at the succeeding stage.
AD conversion is performed as follows. First, a pixel signal voltage Vx is read out by the column AD conversion section 26 from the unit pixel 3 via a vertical signal line 19. The comparison section 252 compares the pixel signal voltage Vx against the reference signal SLP_ADC supplied from the reference signal generation section 27, supplying the comparison result to the latch LT_00 at the first stage of the counter section 254. The latch LT_00 is also supplied with the internal clock CKX from the PLL circuit 20x. The counter section 254 counts when the comparison result of the counter section 254 is high. AD conversion is achieved by obtaining the count result as digital data of the pixel signal voltage Vx. That is, an AD converter is provided for each column. The pixel signal voltage Vx (analog signal) of each of the unit pixels 3 in the selected row is collectively read out into one of the vertical signal lines 19, allowing reset and signal levels of the pixel signal voltage Vx to be directly converted into digital data.
In Patent Document 1, the difference is calculated between the AD-converted reset and signal levels at the same time during the AD conversion. The reference signal comparison AD conversion is performed on a column-by-column basis to perform CDS (Correlated Double Sampling) in the digital domain. This eliminates disadvantages resulting from the CDS in the analog domain, allowing for highly accurate noise removal. Further, this column AD scheme processes one row at a time in the horizontal direction on the screen, eliminating the need for high frequency driving for horizontal scan. As a result, only a low vertical scan frequency is required for AD conversion, providing advantages including easy separation of noise component that develops in a high frequency band from signal component.    Patent Document 1: Japanese Patent Laid-Open No. 2005-328135